AMIC110 Datasheet, PDF (164/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.3.4.1 Two DDR3 Devices
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as
one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a
pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 7-38 shows the topology of the CK net classes and Figure 7-39 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR3 Differential CK Input Buffers
+–
+–
AMIC110
+
Differential Clock
Output Buffer
–
Clock Parallel
Terminator
Rcp
VDDS_DDR
A1
A2
A3
AT
Cac
Rcp
0.1 µF
A1
A2
A3
AT
Routed as Differential Pair
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Figure 7-38. CK Topology for Two DDR3 Devices
DDR3 Address and Control Input Buffers
AMIC110
Address and Control
Output Buffer
Address and Control
Terminator
Rtt
A1
A2
A3
AT
Vtt
Copyright © 2016, Texas Instruments Incorporated
Figure 7-39. ADDR_CTRL Topology for Two DDR3 Devices
7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 7-40 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 7-41
shows the corresponding ADDR_CTRL routing.
164 Peripheral Information and Timings
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