AMIC110 Datasheet, PDF (189/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Table 7-69. Switching Characteristics for MMC[x]_CLK
(see Figure 7-64)
NO.
PARAMETER
STANDARD MODE
MIN TYP MAX
HIGH-SPEED MODE
UNIT
MIN TYP MAX
ƒ_op(CLK)
5
t_cop(CLK)
f_id(CLK)
t_cid(CLK)
6 t_w(CLKL)
Operating frequency, MMC_CLK
Operating period: MMC_CLK
Identification mode frequency, MMC_CLK
Identification mode period: MMC_CLK
Pulse duration, MMC_CLK low
7 t_w(CLKH)
Pulse duration, MMC_CLK high
8 t_r(CLK)
Rise time, all signals (10% to 90%)
9 t_f(CLK)
Fall time, all signals (10% to 90%)
(1) P = MMC_CLK period
41.7
2500
(0.5 × P) –
t_f(CLK)(1)
(0.5 × P) –
t_r(CLK)(1)
24
20.8
400
2500
(0.5 × P) –
t_f(CLK)(1)
(0.5 × P) –
t_r(CLK)(1)
2.2
2.2
48 MHz
ns
400 kHz
ns
ns
ns
2.2 ns
2.2 ns
RMII[x]_REFCLK
(Input)
5
6
7
Figure 7-64. MMC[x]_CLK Timing
8
9
Table 7-70. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
(see Figure 7-65)
NO.
PARAMETER
OPP100
MIN TYP
MAX
OPP50
MIN TYP
UNIT
MAX
10 t_d(CLKL-CMD)
Delay time, MMC_CLK falling clock
edge to MMC_CMD transition
–4
14
–4
17.5 ns
11 t_d(CLKL-DAT)
Delay time, MMC_CLK falling clock
edge to MMC_DATx transition
–4
14
–4
17.5 ns
10
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
11
Figure 7-65. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—Standard Mode
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Peripheral Information and Timings 189