AMIC110 Datasheet, PDF (35/214 Pages) Texas Instruments – Sitara Processors

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ZCZ BALL
NUMBER [1]
PIN NAME [2]
A17
SPI0_SCLK
A16
SPI0_CS0
C15
SPI0_CS1
B17
SPI0_D0
AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Table 4-4. Pin Attributes (ZCZ Package) (continued)
SIGNAL NAME [3]
spi0_sclk
uart2_rxd
I2C2_SDA
ehrpwm0A
pr1_uart0_cts_n
pr1_edio_sof
EMU2
gpio0_2
spi0_cs0
mmc2_sdwp
I2C1_SCL
ehrpwm0_synci
pr1_uart0_txd
pr1_edio_data_in1
pr1_edio_data_out1
gpio0_5
spi0_cs1
uart3_rxd
mmc0_pow
xdma_event_intr2
mmc0_sdcd
EMU4
gpio0_6
spi0_d0
uart2_txd
I2C2_SCL
ehrpwm0B
pr1_uart0_rts_n
pr1_edio_latch_in
EMU3
gpio0_3
MODE [4]
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
3
4
5
6
7
TYPE [5]
BALL RESET
STATE [6]
BALL RESET
REL. STATE
[7]
RESET REL.
MODE [8]
ZCZ POWER [9] HYS [10]
BUFFER
STRENGTH
(mA) [11]
I/O
Z
H
7
VDDSHV6
Yes
6
I
I/OD
O
I
O
I/O
I/O
I/O
Z
H
7
VDDSHV6
Yes
6
I
I/OD
I
O
I
O
I/O
I/O
Z
H
7
VDDSHV6
Yes
6
I
O
I
I
I/O
I/O
I/O
Z
H
7
VDDSHV6
Yes
6
O
I/OD
O
O
I
I/O
I/O
PULLUP
/DOWN TYPE
[12]
I/O CELL [13]
PU/PD
LVCMOS
PU/PD
LVCMOS
PU/PD
LVCMOS
PU/PD
LVCMOS
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Terminal Configuration and Functions
35