AMIC110 Datasheet, PDF (71/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Table 5-8. Valid Combinations of VDD_CORE and
VDD_MPU OPPs for ZCZ Package With Device
Revision Code "A" or Newer
VDD_CORE
OPP50
OPP50
OPP100
OPP100
OPP100
OPP100
OPP100
VDD_MPU
OPP50
OPP100
OPP50
OPP100
OPP120
Turbo
Nitro
Table 5-9. VDD_CORE OPPs for ZCE Package
With Device Revision Code "A" or Newer⁽¹⁾
VDD_CORE
VDD_MPU⁽²⁾
OPP
Rev "A" or
MIN
newer
NOM
MAX
ARM (A8)
DDR3,
DDR3L⁽³⁾
DDR2⁽³⁾
mDDR⁽³⁾
L3 and L4
OPP100
1.056 V
1.100 V
1.144 V
600 MHz
400 MHz
266 MHz
200 MHz
200 and 100
MHz
OPP100
1.056 V
1.100 V
1.144 V
300 MHz
400 MHz
266 MHz
200 MHz
200 and 100
MHz
OPP50
0.912 V
0.950 V
0.988 V
300 MHz
–
125 MHz
90 MHz
100 and 50
MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
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