AMIC110 Datasheet, PDF (170/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.3.6 Routing Specification
7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the AMIC110 device and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 7-52 shows this distance for
two loads. The specifications on the lengths of the transmission lines for the address bus are determined
from this distance. CACLM is determined similarly for other address bus configurations; that is, it is based
on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these
specifications are contained in Table 7-51.
A8^(A)
CACLMX
CACLMY
A8^(A)
A8^(A)
Rtt
A2
A3
AT
Vtt
=
A. It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the
DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net
class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control.
The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Nonincluded lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 7-52. CACLM for Two Address Loads on One Side of PCB
NO.
1 A1 + A2 length
2 A1 + A2 skew
3 A3 length
4 A3 skew⁽⁴⁾
5 A3 skew⁽⁵⁾
6 AS length
Table 7-51. CK and ADDR_CTRL Routing Specification^(1)(2)(3)
PARAMETER
MIN
TYP
MAX
2500
25
660
25
125
100
UNIT
mils
mils
mils
mils
mils
mils
170 Peripheral Information and Timings
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