AMIC110 Datasheet, PDF (128/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
Table 7-13 and Table 7-14 assume testing over the recommended operating conditions and electrical
characteristic conditions shown in Table 7-12 (see Figure 7-14 through Figure 7-17).
Table 7-12. GPMC and NAND Flash Timing Conditions—Asynchronous Mode
PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance
MIN TYP
1
1
3
MAX
5
5
30
UNIT
ns
ns
pF
Table 7-13. GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode⁽¹⁾⁽²⁾
OPP100
OPP50
NO.
MIN
MAX
MIN
MAX
GNFI1
Delay time, output data gpmc_ad[15:0] generation from internal
functional clock GPMC_FCLK⁽³⁾
6.5
6.5
GNFI2
Delay time, input data gpmc_ad[15:0] capture from internal functional
clock GPMC_FCLK⁽³⁾
4.0
4.0
GNFI3
Delay time, output chip select gpmc_csn[x] generation from internal
functional clock GPMC_FCLK⁽³⁾
6.5
6.5
Delay time, output address valid and address latch enable
GNFI4 gpmc_advn_ale generation from internal functional clock
GPMC_FCLK⁽³⁾
6.5
6.5
Delay time, output lower-byte enable and command latch enable
GNFI5 gpmc_be0n_cle generation from internal functional clock
GPMC_FCLK⁽³⁾
6.5
6.5
GNFI6
Delay time, output enable gpmc_oen generation from internal functional
clock GPMC_FCLK⁽³⁾
6.5
6.5
GNFI7
GNFI8
Delay time, output write enable gpmc_wen generation from internal
functional clock GPMC_FCLK⁽³⁾
Skew, functional clock GPMC_FCLK⁽³⁾
6.5
6.5
100
100
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
UNIT
ns
ns
ns
ns
ns
ns
ns
ps
Table 7-14. GPMC and NAND Flash Timing Requirements—Asynchronous Mode
NO.
GNF12⁽¹⁾ t_acc(d)
Access time, input data gpmc_ad[15:0]
OPP100
MIN
MAX
J⁽²⁾
OPP50
MIN
MAX
J⁽²⁾
UNIT
ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽³⁾
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
128 Peripheral Information and Timings
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