AMIC110 Datasheet, PDF (197/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
1
2
4
3
MDIO_CLK
4
Figure 7-78. PRU-ICSS MDIO_CLK Timing
(see Figure 7-79)
NO.
1
t_d(MDC-MDIO)
Table 7-87. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
Delay time, MDC high to MDIO valid
MIN
TYP
10
1
MDIO_CLK (Output)
MAX
390
UNIT
ns
MDIO_DATA (Output)
Figure 7-79. PRU-ICSS MDIO_DATA Timing – Output Mode
7.14.3.2 PRU-ICSS MII_RT Electrical Data and Timing
NOTE
In order to guarantee the MII_RT I/O timing values published in the device data manual, the
PRU ocp_clk clock must be configured for 200 MHz (default value) and the TX_CLK_DELAY
bit field in the PRUSS_MII_RT_TXCFG0/1 register must be set to 6 h (non-default value).
(see Figure 7-80)
NO.
1
t_{c(RX_CLK)}
2
t_{w(RX_CLKH)}
3
t_{w(RX_CLKL)}
4
t_{t(RX_CLK)}
Table 7-88. PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
Cycle time, RX_CLK
Pulse duration, RX_CLK high
Pulse duration, RX_CLK low
Transition time, RX_CLK
MIN
399.96
140
140
10 Mbps
TYP
1
2
MAX
400.04
260
260
3
100 Mbps
MIN
TYP
39.996
14
14
3
MAX
40.004
26
26
3
4
UNIT
ns
ns
ns
ns
MII_RXCLK
4
Figure 7-80. PRU-ICSS MII_RXCLK Timing
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Peripheral Information and Timings 197