AMIC110 Datasheet, PDF (68/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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(6) Not available on the ZCE package.
(7) This terminal is connected to a fail-safe I/O and does not have a dependence on any I/O supply voltage.
(8) This parameter applies to all I/O terminals which are not fail-safe and the requirement applies to all values of I/O supply voltage. For
example, if the voltage applied to a specific I/O supply is 0 volts the valid input voltage range for any I/O powered by that supply will be
–0.5 to +0.3 V. Apply special attention anytime peripheral devices are not powered from the same power sources used to power the
respective I/O supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including
power supply ramp-up and ramp-down sequences.
(9) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal
should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to
any external voltage source.
(10) Based on JEDEC JESD78D [IC Latch-Up Test].
(11) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
Fail-safe I/O terminals are designed such they do not have dependencies on the respective I/O power
supply voltage. This allows external voltage sources to be connected to these I/O terminals when the
respective I/O power supplies are turned off. The USB0_VBUS and USB1_VBUS are the only fail-safe I/O
terminals. All other I/O terminals are not fail-safe and the voltage applied to them should be limited to the
value defined by the steady state max. Voltage at all I/O pins parameter in Section 5.1.
5.2 ESD Ratings
V_ESD
Electrostatic discharge
(ESD) performance:
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾
Charged Device Model (CDM), per JESD22-C101⁽²⁾
VALUE
±2000
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
68
Specifications
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