AMIC110 Datasheet, PDF (154/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.3 DDR3 and DDR3L Routing Guidelines
NOTE
All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise
noted.
7.7.2.3.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 7-41 and
Figure 7-32.
Table 7-41. Switching Characteristics for DDR3 Memory Interface
NO.
PARAMETER
MIN
MAX UNIT
1
t_{c(DDR_CK)}
t_{c(DDR_CKn)}
Cycle time, DDR_CK and DDR_CKn
2.5
3.3⁽¹⁾
ns
(1) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory
devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.
1
DDR_CK
DDR_CKn
Figure 7-32. DDR3 Memory Interface Clock Timing
7.7.2.3.1.1 DDR3 versus DDR2
This specification only covers AMIC110 PCB designs that use DDR3 memory. Designs using DDR2
memory should use the DDR2 routing guidleines described in Section 7.7.2.2. While similar, the two
memory systems have different requirements. It is currently not possible to design one PCB that meets
the requirements of both DDR2 and DDR3.
7.7.2.3.2 DDR3 Device Combinations
Because there are several possible combinations of device counts and single-side or dual-side mounting,
Table 7-42 summarizes the supported device configurations.
Table 7-42. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
16
N
16
2
8
Y ⁽¹⁾
16
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
7.7.2.3.3 DDR3 Interface
This section provides the timing specification for the DDR3 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR3 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR3
specification, see Understanding TI's PCB Routing Rule-Based DDR Timing Specification. This application
report provides generic guidelines and approach. All the specifications provided in the data manual take
precedence over the generic guidelines and must be adhered to for a reliable DDR3 interface operation.
154 Peripheral Information and Timings
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