AMIC110 Datasheet, PDF (162/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.3.3.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, the AMIC110 device
DDR3 power, and the AMIC110 device DDR3 ground connections. Table 7-48 contains the specification
for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is
good to:
• Fit as many HS bypass capacitors as possible.
• Minimize the distance from the bypass capacitor to the power terminals being bypassed.
• Use the smallest physical sized capacitors possible with the highest capacitance readily available.
• Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
• Minimize via sharing. Note the limits on via sharing shown in Table 7-48.
Table 7-48. High-Speed Bypass Capacitors
NO.
PARAMETER
1 HS bypass capacitor package size⁽¹⁾
MIN
TYP
MAX UNIT
0201
0402 10 mils
2
Distance, HS bypass capacitor to AMIC110 VDDS_DDR and VSS terminal
being bypassed^(2)(3)(4)
400 mils
3 AMIC110 VDDS_DDR HS bypass capacitor count
20
devices
4 AMIC110 VDDS_DDR HS bypass capacitor total capacitance
1
μF
5
Trace length from AMIC110 VDDS_DDR and VSS terminal to connection
via⁽²⁾
6 Distance, HS bypass capacitor to DDR3 device being bypassed⁽⁵⁾
7 DDR3 device HS bypass capacitor count⁽⁶⁾
8 DDR3 device HS bypass capacitor total capacitance⁽⁶⁾
9 Number of connection vias for each HS bypass capacitor⁽⁷⁾⁽⁸⁾
10 Trace length from bypass capacitor connect to connection via⁽²⁾⁽⁸⁾
12
0.85
2
35
70 mils
150 mils
devices
μF
vias
35
100 mils
11
Number of connection vias for each DDR3 device power and ground
terminal⁽⁹⁾
1
vias
12
Trace length from DDR3 device power and ground terminal to connection
via⁽²⁾⁽⁷⁾
35
60 mils
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer and shorter is better.
(3) Measured from the nearest AMIC110 VDDS_DDR and ground terminal to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the AMIC110 device, between the cluster of VDDS_DDR and ground terminals,
between the DDR3 interfaces on the package.
(5) Measured from the DDR3 device power and ground terminal to the center of the capacitor package.
(6) Per DDR3 device.
(7) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(8) An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be used for
the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils.
(9) Up to two pairs of DDR3 power and ground terminals may share a via.
7.7.2.3.3.7.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
162 Peripheral Information and Timings
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