AMIC110 Datasheet, PDF (111/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Table 7-7. GPMC and NOR Flash Switching Characteristics—Synchronous Mode⁽²⁾
NO.
F0 1 / t_c(clk)
F1 t_w(clkH)
F1 t_w(clkL)
t_dc(clk)
t_J(clk)
t_R(clk)
t_F(clk)
t_R(do)
t_F(do)
F2
t_d(clkH-csnV)
F3
t_{d(clkH-csnIV)}
F4 t_d(aV-clk)
F5
t_d(clkH-aIV)
F6
t_{d(be[x]nV-clk)}
F7
t_{d(clkH-be[x]nIV)}
F7
t_{d(clkL-be[x]nIV)}
F7
t_{d(clkL-be[x]nIV)}
F8
t_d(clkH-advn)
F9
t_{d(clkH-advnIV)}
F10 t_d(clkH-oen)
F11 t_{d(clkH-oenIV)}
F14 t_d(clkH-wen)
F15 t_d(clkH-do)
F15 t_d(clkL-do)
F15 t_d(clkL-do)
F17 t_{d(clkH-be[x]n)}
F17 t_{d(clkL-be[x]n)}
F17 t_{d(clkL-be[x]n)}
PARAMETER
Frequency⁽¹⁸⁾, output clock gpmc_clk
Typical pulse duration, output clock gpmc_clk high
Typical pulse duration, output clock gpmc_clk low
Duty cycle error, output clock gpmc_clk
Jitter standard deviation⁽¹⁹⁾, output clock gpmc_clk
Rise time, output clock gpmc_clk
Fall time, output clock gpmc_clk
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_csn[x]⁽¹⁴⁾ transition
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_csn[x]⁽¹⁴⁾ invalid
Delay time, output address gpmc_a[27:1] valid to
output clock gpmc_clk first edge
Delay time, output clock gpmc_clk rising edge to
output address gpmc_a[27:1] invalid
Delay time, output lower byte enable and command
latch enable gpmc_be0n_cle, output upper byte
enable gpmc_be1n valid to output clock gpmc_clk
first edge
Delay time, output clock gpmc_clk rising edge to
output lower byte enable and command latch enable
gpmc_be0n_cle, output upper byte enable
gpmc_be1n invalid⁽¹¹⁾
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 invalid⁽¹²⁾
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 invalid⁽¹³⁾
Delay time, output clock gpmc_clk rising edge to
output address valid and address latch enable
gpmc_advn_ale transition
Delay time, output clock gpmc_clk rising edge to
output address valid and address latch enable
gpmc_advn_ale invalid
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_oen transition
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_oen invalid
Delay time, output clock gpmc_clk rising edge to
output write enable gpmc_wen transition
Delay time, output clock gpmc_clk rising edge to
output data gpmc_ad[15:0] transition⁽¹¹⁾
Delay time, gpmc_clk falling edge to gpmc_ad[15:0]
data bus transition⁽¹²⁾
Delay time, gpmc_clk falling edge to gpmc_ad[15:0]
data bus transition⁽¹³⁾
Delay time, output clock gpmc_clk rising edge to
output lower byte enable and command latch enable
gpmc_be0n_cle transition⁽¹¹⁾
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 transition⁽¹²⁾
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 transition⁽¹³⁾
OPP100
MIN
MAX
0.5P⁽¹⁵⁾
0.5P⁽¹⁵⁾
100
0.5P⁽¹⁵⁾
0.5P⁽¹⁵⁾
–500
500
33.33
2
2
2
2
F⁽⁶⁾ - 2.2 F⁽⁶⁾ + 4.5
E⁽⁵⁾ – 2.2 E⁽⁵⁾ + 4.5
B⁽²⁾ – 4.5 B⁽²⁾ + 2.3
–2.3
4.5
B⁽²⁾ – 1.9 B⁽²⁾ + 2.3
D⁽⁴⁾ – 2.3 D⁽⁴⁾ + 1.9
D⁽⁴⁾ – 2.3 D⁽⁴⁾ + 1.9
D⁽⁴⁾ – 2.3 D⁽⁴⁾ + 1.9
G⁽⁷⁾ – 2.3 G⁽⁷⁾ + 4.5
D⁽⁴⁾ – 2.3 D⁽⁴⁾ + 3.5
H⁽⁸⁾ – 2.3 H⁽⁸⁾ + 3.5
E⁽⁸⁾ – 2.3 E⁽⁸⁾ + 3.5
I⁽⁹⁾ – 2.3 I⁽⁹⁾ + 4.5
J⁽¹⁰⁾ – 2.3 J⁽¹⁰⁾ + 1.9
J⁽¹⁰⁾ – 2.3 J⁽¹⁰⁾ + 1.9
J⁽¹⁰⁾ – 2.3 J⁽¹⁰⁾ + 1.9
J⁽¹⁰⁾ – 2.3 J⁽¹⁰⁾ + 1.9
J⁽¹⁰⁾ – 2.3 J⁽¹⁰⁾ + 1.9
J⁽¹⁰⁾ – 2.3 J⁽¹⁰⁾ + 1.9
OPP50
MIN
MAX
0.5P⁽¹⁵⁾
0.5P⁽¹⁵⁾
50
0.5P⁽¹⁵⁾
0.5P⁽¹⁵⁾
–500
500
33.33
2
2
2
2
F⁽⁶⁾ - 3.2 F⁽⁶⁾ + 9.5
E⁽⁵⁾ – 3.2 E⁽⁵⁾ + 9.5
B⁽²⁾ – 5.5 B⁽²⁾ + 12.3
–3.3
14.5
B⁽²⁾ – 2.9 B⁽²⁾ + 12.3
D⁽⁴⁾ – 3.3 D⁽⁴⁾ + 6.9
D⁽⁴⁾ – 3.3 D⁽⁴⁾ + 6.9
D⁽⁴⁾ – 3.3 D⁽⁴⁾ + 11.9
G⁽⁷⁾ – 3.3 G⁽⁷⁾ + 9.5
D⁽⁴⁾ – 3.3 D⁽⁴⁾ + 9.5
H⁽⁸⁾ – 3.3 H⁽⁸⁾ + 8.5
E⁽⁸⁾ – 3.3 E⁽⁸⁾ + 8.5
I⁽⁹⁾ – 3.3
I⁽⁹⁾ + 9.5
J⁽¹⁰⁾ – 3.3 J⁽¹⁰⁾ + 6.9
J⁽¹⁰⁾ – 3.3 J⁽¹⁰⁾ + 6.9
J⁽¹⁰⁾ – 3.3 J⁽¹⁰⁾ + 11.9
J⁽¹⁰⁾ – 3.3 J⁽¹⁰⁾ + 6.9
J⁽¹⁰⁾ – 3.3 J⁽¹⁰⁾ + 6.9
J⁽¹⁰⁾ – 3.3 J⁽¹⁰⁾ + 11.9
UNIT
MHz
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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