AMIC110 Datasheet, PDF (70/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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Table 5-4. Valid Combinations of VDD_CORE and VDD_MPU OPPs for ZCZ Package
With Device Revision Code "Blank"
NOTE
Device Revision Code "Blank" is not supported for this family of devices.
Table 5-5. VDD_CORE OPPs for ZCE Package
With Device Revision Code "Blank"
NOTE
Device Revision Code "Blank" is not supported for this family of devices.
Table 5-6. VDD_CORE OPPs for ZCZ Package
With Device Revision Code "A" or Newer⁽¹⁾
VDD_CORE
VDD_CORE
OPP
Rev "A" or
MIN
Newer
NOM
MAX
DDR3,
DDR3L⁽²⁾
DDR2⁽²⁾
mDDR⁽²⁾
L3 and L4
OPP100
1.056 V
1.100 V
1.144 V
400 MHz
266 MHz
200 MHz
200 and 100
MHz
OPP50
0.912 V
0.950 V
0.988 V
—
125 MHz
90 MHz
100 and 50
MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
Table 5-7. VDD_MPU OPPs for ZCZ Package
With Device Revision Code "A" or Newer⁽¹⁾
VDD_MPU OPP
MIN
VDD_MPU
NOM
Nitro
1.272 V
1.325 V
Turbo
1.210 V
1.260 V
OPP120
OPP100⁽²⁾
OPP100⁽³⁾
1.152 V
1.056 V
1.056 V
1.200 V
1.100 V
1.100 V
OPP50
0.912 V
0.950 V
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Applies to all orderable AM335__ZCZ_60 (600-MHz speed grade) or higher devices.
(3) Applies to all orderable AM335__ZCZ_30 (300-MHz speed grade) devices.
MAX
1.378 V
1.326 V
1.248 V
1.144 V
1.144 V
0.988 V
ARM (A8)
1 GHz
800 MHz
720 MHz
600 MHz
300 MHz
300 MHz
70
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