AMIC110 Datasheet, PDF (63/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
4.3.6.4 McASP
SIGNAL NAME [1]
mcasp0_aclkr
mcasp0_aclkx
mcasp0_ahclkr
mcasp0_ahclkx
mcasp0_axr0
mcasp0_axr1
mcasp0_axr2
mcasp0_axr3
mcasp0_fsr
mcasp0_fsx
Table 4-46. McASP/MCASP0 Signals Description
DESCRIPTION [2]
McASP0 Receive Bit Clock
McASP0 Transmit Bit Clock
McASP0 Receive Master Clock
McASP0 Transmit Master Clock
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Receive Frame Sync
McASP0 Transmit Frame Sync
TYPE [3]
ZCZ BALL [4]
I/O
B12, J17, U18, V2
I/O
A13, K18, U1, V16
I/O
C12, U4
I/O
A14, K15, T5
I/O
D12, L17, T16, U3
I/O
D13, L16, V17, V4
I/O
B12, C12, H16, U4,
V2
I/O
A14, C13, M16, T5,
V3
I/O
C13, J18, V12, V3
I/O
B13, L18, U16, U2
SIGNAL NAME [1]
mcasp1_aclkr
mcasp1_aclkx
mcasp1_ahclkr
mcasp1_ahclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_fsr
mcasp1_fsx
Table 4-47. McASP/MCASP1 Signals Description
DESCRIPTION [2]
McASP1 Receive Bit Clock
McASP1 Transmit Bit Clock
McASP1 Receive Master Clock
McASP1 Transmit Master Clock
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Receive Frame Sync
McASP1 Transmit Frame Sync
TYPE [3]
ZCZ BALL [4]
I/O
K17, M16
I/O
B12, H17, J17
I/O
M16
I/O
H18, M16
I/O
D13, J16, K15
I/O
A14, K16
I/O
H16, K17
I/O
H18, L15
I/O
K16, L15
I/O
C13, J15, J18
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Terminal Configuration and Functions
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