AMIC110 Datasheet, PDF (123/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
GPMC_FCLK
gpmc_clk
gpmc_csn[x]
gpmc_a[10:1]
gpmc_be0n_cle
gpmc_be1n
FA5
FA1
FA9
FA10
FA10
Address 0
FA0
Valid
FA0
Valid
FA16
FA9
FA10
FA10
FA5
FA1
Address 1
FA0
Valid
FA0
Valid
gpmc_advn_ale
gpmc_oen
gpmc_ad[15:0]
FA3
FA12
FA4
FA13
FA3
FA12
FA4
FA13
Data Upper
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-9. GPMC and NOR Flash—Asynchronous Read—32-Bit
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Peripheral Information and Timings 123