AMIC110 Datasheet, PDF (3/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
• Device Identification
– Contains Electrical Fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
• Production ID
• Device Part Number (Unique JTAG ID)
• Device Revision (Readable by Host ARM)
• Debug Interface Support
– JTAG and cJTAG for ARM (Cortex-A8 and
PRCM), PRU-ICSS Debug
– Supports Device Boundary Scan
– Supports IEEE 1500
• DMA
– On-Chip Enhanced DMA Controller (EDMA) has
Three Third-Party Transfer Controllers (TPTCs)
and One Third-Party Channel Controller
(TPCC), Which Supports up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
• Transfers to and from On-Chip Memories
1.2 Applications
• Industrial Communications
• Connected Industrial Drives
• Transfers to and from External Storage
(EMIF, GPMC, Slave Peripherals)
• Inter-Processor Communication (IPC)
– Integrates Hardware-Based Mailbox for IPC and
Spinlock for Process Synchronization Between
Cortex-A8, PRCM, and PRU-ICSS
• Mailbox Registers that Generate Interrupts
– Four Initiators (Cortex-A8, PRCM, PRU0,
PRU1)
• Spinlock has 128 Software-Assigned Lock
Registers
• Security
– Secure Boot
• Boot Modes
– Boot Mode is Selected Through Boot
Configuration Pins Latched on the Rising Edge
of the PWRONRSTn Reset Input Pin
• Package:
– 324-Pin S-PBGA-N324 Package
(ZCZ Suffix), 0.80-mm Ball Pitch
• Backplane I/O
1.3 Description
The AMIC110 device is a multiprotocol programmable industrial communications processor providing
ready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as some
masters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interface
options. The device supports high-level operating systems (HLOS). Linux^® and TI-RTOS are available free
of charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessor
is an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.
The AMIC110 microprocessor contains the subsystems shown in Figure 1-1 and a brief description of
each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS is
separate from the ARM core, allowing independent operation and clocking for greater efficiency and
flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as
EtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others.
Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all
system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized
data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor
cores of SoC.
PART NUMBER
Device Information⁽¹⁾
PACKAGE
AMIC110ZCZ
NFBGA (324)
(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.
BODY SIZE
15.0 mm × 15.0 mm
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