AMIC110 Datasheet, PDF (182/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.12 Multichannel Serial Port Interface (McSPI)
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x and
AMIC110 Sitara Processors Technical Reference Manual.
7.12.1 McSPI Electrical Data and Timing
The following timings are applicable to the different configurations of McSPI in master or slave mode for
any McSPI and any channel (n).
7.12.1.1 McSPI—Slave Mode
Table 7-61. McSPI Timing Conditions – Slave Mode
Input Conditions
t_r
Input signal rise time
t_f
Input signal fall time
Output Condition
C_load
Output load capacitance
PARAMETER
MIN
MAX UNIT
5 ns
5 ns
20 pF
Table 7-62. Timing Requirements for McSPI Input Timings—Slave Mode
(see Figure 7-59)
OPP100
OPP50
NO.
UNIT
MIN
MAX
MIN
MAX
1
t_c(SPICLK)
2
t_w(SPICLKL)
Cycle time, SPI_CLK
Typical pulse duration, SPI_CLK low
62.5
0.5P –
3.12⁽¹⁾
0.5P +
3.12⁽¹⁾
124.8
0.5P –
3.12⁽¹⁾
ns
0.5P +
3.12⁽¹⁾
ns
3
t_w(SPICLKH)
Typical pulse duration, SPI_CLK high
0.5P –
3.12⁽¹⁾
0.5P +
3.12⁽¹⁾
0.5P –
3.12⁽¹⁾
0.5P +
3.12⁽¹⁾
ns
4
t_{su(SIMO-SPICLK)}
Setup time, SPI_D[x] (SIMO) valid before SPI_CLK
active edge⁽²⁾⁽³⁾
12.92
12.92
ns
5
t_{h(SPICLK-SIMO)}
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK
active edge⁽²⁾⁽³⁾
12.92
12.92
ns
8
t_{su(CS-SPICLK)}
9
t_h(SPICLK-CS)
(1) P = SPI_CLK period.
Setup time, SPI_CS valid before SPI_CLK first
edge⁽²⁾
Hold time, SPI_CS valid after SPI_CLK last edge⁽²⁾
12.92
12.92
12.92
ns
12.92
ns
(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 7-63. Switching Characteristics for McSPI Output Timings—Slave Mode
(see Figure 7-60)
NO.
PARAMETER
OPP100
MIN
MAX
OPP50
MIN
UNIT
MAX
6
t_{d(SPICLK-SOMI)}
Delay time, SPI_CLK active edge to
SPI_D[x] (SOMI) transition⁽¹⁾⁽²⁾
–4.00
17.12
–4.00
17.12 ns
7
t_d(CS-SOMI)
Delay time, SPI_CS active edge to
SPI_D[x] (SOMI) transition⁽¹⁾⁽²⁾
17.12
17.12 ns
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
182 Peripheral Information and Timings
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