AMIC110 Datasheet, PDF (44/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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4.3.1 External Memory Interfaces
Table 4-8. External Memory Interfaces/DDR Signals Description
ddr_a0
ddr_a1
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
SIGNAL NAME [1]
ddr_ck
ddr_cke
ddr_csn0
ddr_d0
ddr_d1
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d2
ddr_d3
ddr_d4
ddr_d5
ddr_d6
ddr_d7
ddr_d8
ddr_d9
ddr_dqm0
ddr_dqm1
ddr_dqs0
ddr_dqs1
ddr_dqsn0
ddr_dqsn1
DESCRIPTION [2]
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM COLUMN ADDRESS STROBE OUTPUT
(ACTIVE LOW)
DDR SDRAM CLOCK OUTPUT (Differential+)
DDR SDRAM CLOCK ENABLE OUTPUT
DDR SDRAM CHIP SELECT OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR WRITE ENABLE / DATA MASK FOR DATA[7:0]
DDR WRITE ENABLE / DATA MASK FOR DATA[15:8]
DDR DATA STROBE FOR DATA[7:0] (Differential+)
DDR DATA STROBE FOR DATA[15:8] (Differential+)
DDR DATA STROBE FOR DATA[7:0] (Differential-)
DDR DATA STROBE FOR DATA[15:8] (Differential-)
TYPE [3]
ZCZ BALL [4]
O
F3
O
H1
O
F4
O
F2
O
E3
O
H3
O
H4
O
D3
O
E4
O
C3
O
C2
O
B1
O
D5
O
E2
O
D4
O
C1
O
C4
O
E1
O
B3
O
F1
O
D2
O
G3
O
H2
I/O
M3
I/O
M4
I/O
K2
I/O
K3
I/O
K4
I/O
L3
I/O
L4
I/O
M1
I/O
N1
I/O
N2
I/O
N3
I/O
N4
I/O
P3
I/O
P4
I/O
J1
I/O
K1
O
M2
O
J2
I/O
P1
I/O
L1
I/O
P2
I/O
L2
44
Terminal Configuration and Functions
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