AMIC110 Datasheet, PDF (194/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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Table 7-79. PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN (continued)
(see Figure 7-73)
NO.
6
t_{r(EDIO_DATA_IN)}
t_{f(EDIO_DATA_IN)}
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
MIN
MAX UNIT
1.00
3.00
ns
1.00
3.00
ns
2
3
EDIO_LATCH_IN
1
EDIO_DATA_IN[7:0]
4
5
6
Figure 7-73. PRU-ICSS ECAT Input Validated With LATCH_IN Timing
Table 7-80. PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
(see Figure 7-74)
NO.
MIN
MAX
1
t_{w(EDC_SYNCx_OUT)}
2
t_{r(EDC_SYNCx_OUT)}
3
t_{f(EDC_SYNCx_OUT)}
4
t_{su(EDIO_DATA_IN-}
EDC_SYNCx_OUT)
5
t_{h(EDC_SYNCx_OUT-}
EDIO_DATA_IN)
6
t_{r(EDIO_DATA_IN)}
t_{f(EDIO_DATA_IN)}
Pulse width, EDC_SYNCx_OUT
Rising time, EDC_SYNCx_OUT
Falling time, EDC_SYNCx_OUT
Setup time, EDIO_DATA_IN valid before
EDC_SYNCx_OUT active edge
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT
active edge
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
100.00
1.00
3.00
1.00
3.00
20.00
20.00
1.00
3.00
1.00
3.00
UNIT
ns
ns
ns
ns
ns
ns
ns
2
3
EDC_SYNCx_OUT
1
EDIO_DATA_IN[7:0]
4
5
6
Figure 7-74. PRU-ICSS ECAT Input Validated With SYNCx Timing
194 Peripheral Information and Timings
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