AMIC110 Datasheet, PDF (168/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
Figure 7-46 shows the CK routing for one DDR3 device. Figure 7-47 shows the corresponding
ADDR_CTRL routing.
VDDS_DDR
Rcp
Cac
A2
AT
A2
AT
Rcp
0.1 µF
=
Figure 7-46. CK Routing for One DDR3 Device
Rtt
A2
AT
Vtt
=
Figure 7-47. ADDR_CTRL Routing for One DDR3 Device
7.7.2.3.5 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point single-ended. Figure 7-48
and Figure 7-49 show these topologies.
168 Peripheral Information and Timings
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