AMIC110 Datasheet, PDF (149/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7.7.2.2.2.7 High-Speed (HS) Bypass Capacitors
HS bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to
minimize the parasitic series inductance of the HS bypass capacitors, the AMIC110 device DDR2 power,
and the AMIC110 device DDR2 ground connections. Table 7-34 contains the specification for the HS
bypass capacitors as well as for the power connections on the PCB.
Table 7-34. HS Bypass Capacitors
NO.
PARAMETER
1 HS bypass capacitor package size⁽¹⁾
MIN
MAX
0402
2 Distance from HS bypass capacitor to device being bypassed
3 Number of connection vias for each HS bypass capacitor⁽²⁾
250
2
4 Trace length from bypass capacitor contact to connection via
30
5 Number of connection vias for each AMIC110 VDDS_DDR and VSS terminal
1
6 Trace length from AMIC110 VDDS_DDR and VSS terminal to connection via
35
7 Number of connection vias for each DDR2 device power and ground terminal
1
8 Trace length from DDR2 device power and ground terminal to connection via
9 AMIC110 VDDS_DDR HS bypass capacitor count⁽³⁾
35
10
10 AMIC110 VDDS_DDR HS bypass capacitor total capacitance
0.6
11 DDR2 device HS bypass capacitor count⁽³⁾⁽⁴⁾
8
12 DDR2 device HS bypass capacitor total capacitance⁽⁴⁾
0.4
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per DDR2 device.
UNIT
10 mils
mils
vias
mils
vias
mils
vias
mils
devices
μF
devices
μF
7.7.2.2.2.8 Net Classes
Table 7-35 lists the clock net classes for the DDR2 interface. Table 7-36 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
SIGNAL NET CLASS
ADDR_CTRL
DQ0
DQ1
Table 7-35. Clock Net Class Definitions
CLOCK NET CLASS
CK
DQS0
DQS1
AMIC110 PIN NAMES
DDR_CK and DDR_CKn
DDR_DQS0 and DDR_DQSn0
DDR_DQS1 and DDR_DQSn1
Table 7-36. Signal Net Class Definitions
ASSOCIATED CLOCK
NET CLASS
CK
DQS0
DQS1
AMIC110 PIN NAMES
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
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Peripheral Information and Timings 149