AMIC110 Datasheet, PDF (195/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Table 7-81. PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
(see Figure 7-75)
NO.
1
t_{w(EDIO_SOF)}
Pulse duration, EDIO_SOF
2
t_{r(EDIO_SOF)}
Rising time, EDIO_SOF
3
t_{f(EDIO_SOF)}
Falling time, EDIO_SOF
4
t_{su(EDIO_DATA_IN-}
EDIO_SOF)
Setup time, EDIO_DATA_IN valid before EDIO_SOF
active edge
5
t_{h(EDIO_SOF-EDIO_DATA_IN)}
Hold time, EDIO_DATA_IN valid after EDIO_SOF active
edge
MIN
4 × P ⁽¹⁾
1.00
1.00
20.00
20.00
MAX
5 × P⁽¹⁾
3.00
3.00
UNIT
ns
ns
ns
ns
ns
6
t_{r(EDIO_DATA_IN)}
t_{f(EDIO_DATA_IN)}
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
3.00
ns
1.00
3.00
ns
(1) P = PRU-ICSS IEP clock source period.
2
3
EDIO_SOF
1
EDIO_DATA_IN[7:0]
4
5
6
Figure 7-75. PRU-ICSS ECAT Input Validated With SOF
Table 7-82. PRU-ICSS ECAT Timing Requirements - LATCHx_IN
(see Figure 7-76)
NO.
1
2
3
t_{w(EDC_LATCHx_IN)}
t_{r(EDC_LATCHx_IN)}
t_{f(EDC_LATCHx_IN)}
Pulse duration, EDC_LATCHx_IN
Rising time, EDC_LATCHx_IN
Falling time, EDC_LATCHx_IN
MIN
3 × P ⁽¹⁾
1.00
1.00
(1) P = PRU-ICSS IEP clock source period.
2
3
EDC_LATCHx_IN
1
Figure 7-76. PRU-ICSS ECAT LATCHx_IN Timing
MAX
3.00
3.00
UNIT
ns
ns
ns
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