AMIC110 Datasheet, PDF (139/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7.7.2.1.2.9 LPDDR Signal Termination
There is no specific need for adding terminations on the LPDDR interface. However, system designers
may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial
terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis.
Placement of serial terminations for ADDR_CTRL net class signals should be close to the AMIC110
device. Table 7-25 shows the specifications for the serial terminators in such cases.
Table 7-25. LPDDR Signal Terminations
NO.
1 CK net class⁽¹⁾
2 ADDR_CTRL net class^(1)(3)(4)
PARAMETER
3 DQS0, DQS1, DQ0, and DQ1 net classes
(1) Only series termination is permitted.
(2) Zo is the LPDDR PCB trace characteristic impedance.
(3) Series termination values larger than typical only recommended to address EMI issues.
(4) Series termination values should be uniform across net class.
MIN
TYP
MAX UNIT
0
22
Zo⁽²⁾ Ω
0
22
Zo⁽²⁾ Ω
0
22
Zo⁽²⁾ Ω
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Peripheral Information and Timings 139