AMIC110 Datasheet, PDF (152/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
Figure 7-30 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of
signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length
A is the majority of the total length of signal path AB and AC.
A1
T
A
AMIC110
A1
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Figure 7-30. CK and ADDR_CTRL Routing and Topology
Table 7-39. CK and ADDR_CTRL Routing Specification⁽¹⁾⁽²⁾
NO.
PARAMETER
MIN
TYP
MAX UNIT
1 Center-to-center CK spacing
2 CK differential pair skew length mismatch⁽²⁾⁽³⁾
2w
25 mils
3 CK B-to-CK C skew length mismatch
4 Center-to-center CK to other DDR2 trace spacing⁽⁴⁾
5 CK and ADDR_CTRL nominal trace length⁽⁵⁾
4w
CACLM-50
25 mils
CACLM
CACLM+50 mils
6 ADDR_CTRL-to-CK skew length mismatch
100 mils
7 ADDR_CTRL-to-ADDR_CTRL skew length mismatch
8 Center-to-center ADDR_CTRL to other DDR2 trace spacing⁽⁴⁾
4w
9 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing⁽⁴⁾
3w
10 ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch⁽²⁾
100 mils
100 mils
11 ADDR_CTRL B-to-C skew length mismatch
100 mils
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) Series terminator, if used, should be located closest to the AMIC110 device.
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 7-31.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 7-31 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
A1
DQ[0]
DQ[1]
AMIC110
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Figure 7-31. DQS[x] and DQ[x] Routing and Topology
152 Peripheral Information and Timings
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