AMIC110 Datasheet, PDF (196/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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Table 7-83. PRU-ICSS ECAT Switching Requirements - Digital I/Os
NO.
PARAMETER
1
t_{w(EDIO_OUTVALID)}
2
t_{r(EDIO_OUTVALID)}
3
t_{f(EDIO_OUTVALID)}
4
t_{d(EDIO_OUTVALID-}
EDIO_DATA_OUT)
5
t_{r(EDIO_DATA_OUT)}
6
t_{f(EDIO_DATA_OUT)}
7
t_{sk(EDIO_DATA_OUT)}
Pulse duration, EDIO_OUTVALID
Rising time, EDIO_OUTVALID
Falling time, EDIO_OUTVALID
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
Rising time, EDIO_DATA_OUT
Falling time, EDIO_DATA_OUT
EDIO_DATA_OUT skew
(1) P = PRU-ICSS IEP clock source period.
MIN
14 × P⁽¹⁾
1.00
1.00
0.00
1.00
1.00
7.14.3 PRU-ICSS MII_RT and Switch
MAX
32 × P⁽¹⁾
3.00
3.00
18 × P⁽¹⁾
3.00
3.00
8.00
UNIT
ns
ns
ns
ns
ns
ns
ns
Table 7-84. PRU-ICSS MII_RT Switch Timing Conditions
PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance
(1) Except when specified otherwise.
MIN TYP
1 ⁽¹⁾
1 ⁽¹⁾
3
7.14.3.1 PRU-ICSS MDIO Electrical Data and Timing
MAX UNIT
3 ⁽¹⁾
ns
3 ⁽¹⁾
ns
20 pF
(see Figure 7-77)
NO.
1
t_su(MDIO-MDC)
2
t_h(MDIO-MDC)
Table 7-85. PRU-ICSS MDIO Timing Requirements – MDIO_DATA
Setup time, MDIO valid before MDC high
Hold time, MDIO valid from MDC high
MIN
TYP
90
0
MAX
UNIT
ns
ns
1
2
MDIO_CLK (Output)
MDIO_DATA (Input)
Figure 7-77. PRU-ICSS MDIO_DATA Timing - Input Mode
(see Figure 7-78)
NO.
1
t_c(MDC)
2
t_w(MDCH)
3
t_w(MDCL)
4
t_t(MDC)
Table 7-86. PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
PARAMETER
Cycle time, MDC
Pulse duration, MDC high
Pulse duration, MDC low
Transition time, MDC
MIN TYP
400
160
160
MAX
5
UNIT
ns
ns
ns
ns
196 Peripheral Information and Timings
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