AMIC110 Datasheet, PDF (141/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Figure 7-23 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
A1
DQ[0]
DQ[1]
AMIC110
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Figure 7-23. DQS[x] and DQ[x] Routing and Topology
Table 7-27. DQS[x] and DQ[x] Routing Specification⁽¹⁾
NO.
PARAMETER
MIN
TYP
MAX UNIT
1 Center-to-center DQS[x] spacing
2 Center-to-center DDR_DQS[x] to other LPDDR trace spacing⁽²⁾
3 DQS[x] and DQ[x] nominal trace length⁽³⁾
4 DQ[x]-to-DQS[x] skew length mismatch⁽³⁾
5 DQ[x]-to-DQ[x] skew length mismatch⁽³⁾
6 Center-to-center DQ[x] to other LPDDR trace spacing⁽²⁾⁽⁴⁾
7 Center-to-center DQ[x] to other DQ[x] trace spacing⁽²⁾⁽⁵⁾
4w
DQLM-50
4w
3w
2w
DQLM
DQLM+50 mils
100 mils
100 mils
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1 and DQ1.
(4) Signals from one DQ net class should be considered other LPDDR traces to another DQ net class.
(5) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
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Peripheral Information and Timings 141