AMIC110 Datasheet, PDF (73/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
over junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
NOM
MAX UNIT
VDDA_ADC
Supply voltage range for ADC,
analog
1.710
1.800
1.890 V
VDDSHV1
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
1.710
1.800
1.890 V
VDDSHV2⁽⁶⁾
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
1.710
1.800
1.890 V
VDDSHV3⁽⁶⁾
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
1.710
1.800
1.890 V
VDDSHV4
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
1.710
1.800
1.890 V
VDDSHV5
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
1.710
1.800
1.890 V
VDDSHV6
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
1.710
1.800
1.890 V
VDDSHV1
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
3.135
3.300
3.465 V
VDDSHV2⁽⁶⁾
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
3.135
3.300
3.465 V
VDDSHV3⁽⁶⁾
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
3.135
3.300
3.465 V
VDDSHV4
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
3.135
3.300
3.465 V
VDDSHV5
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
3.135
3.300
3.465 V
VDDSHV6
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
3.135
3.300
3.465 V
DDR_VREF
Voltage range for DDR SSTL and
HSTL reference input (DDR2,
0.49 × VDDS_DDR 0.50 × VDDS_DDR 0.51 × VDDS_DDR
V
DDR3, DDR3L)
USB0_VBUS
Voltage range for USB VBUS
comparator input
0.000
5.000
5.250 V
USB1_VBUS⁽⁶⁾
Voltage range for USB VBUS
comparator input
0.000
5.000
5.250 V
USB0_ID
Voltage range for the USB ID
input
(7)
V
USB1_ID⁽⁶⁾
Voltage range for the USB ID
input
(7)
V
Commercial temperature
0
Operating temperature
range, T_J
Industrial temperature
–40
Extended temperature
–40
90
90 °C
105
(1) The supply voltage defined by OPP100 should be applied to this power domain before the device is released from reset.
(2) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(4) VDDS should be supplied irrespective of 1.8- or 3.3-V mode of operation of the dual-voltage I/Os.
(5) For more details on power supply requirements, see Section 6.1.4.
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Specifications
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