AMIC110 Datasheet, PDF (158/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.3.3.2 Compatible JEDEC DDR3 Devices
Table 7-43 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Table 7-43. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
PARAMETER
TEST CONDITIONS
MIN
1 JEDEC DDR3 device speed grade
t_{C(DDR_CK)} and t_{C(DDR_CKn)}
= 3.3 ns
t_{C(DDR_CK)} and t_{C(DDR_CKn)}
= 2.5 ns
DDR3-800
DDR3-1600
2 JEDEC DDR3 device bit width
x8
3 JEDEC DDR3 device count⁽¹⁾
1
(1) For valid DDR3 device configurations and device counts, see Section 7.7.2.3.3.1, Figure 7-33, and Figure 7-35.
MAX UNIT
x16 bits
2 devices
7.7.2.3.3.3 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 7-44.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 7-44. Minimum PCB Stackup⁽¹⁾
LAYER
TYPE
DESCRIPTION
1
Signal
Top signal routing
2
Plane
Ground
3
Plane
Split Power Plane
4
Signal
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross
splits in the power plane.
158 Peripheral Information and Timings
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