AMIC110 Datasheet, PDF (110/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7 External Memory Interfaces
The device includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface (EMIF)
7.7.1 General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem and General-Purpose Memory Controller
section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
The GPMC is the unified memory controller used to interface external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
7.7.1.1 GPMC and NOR Flash—Synchronous Mode
Table 7-6 and Table 7-7 assume testing over the recommended operating conditions and electrical
characteristic conditions shown in Table 7-5 (see Figure 7-3 through Figure 7-7).
Table 7-5. GPMC and NOR Flash Timing Conditions—Synchronous Mode
PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Condition
C_LOAD
Output load capacitance
MIN
TYP
1
1
3
MAX UNIT
5 ns
5 ns
30 pF
Table 7-6. GPMC and NOR Flash Timing Requirements—Synchronous Mode
NO.
F12 t_su(dV-clkH)
Setup time, input data gpmc_ad[15:0] valid before output clock
gpmc_clk high
F13 t_h(clkH-dV)
Hold time, input data gpmc_ad[15:0]
valid after output clock gpmc_clk
high
Industrial extended
temperature
(-40°C to 125°C)
All other temperature ranges
F21
t_{su(waitV-clkH)}
Setup time, input wait gpmc_wait[x]⁽¹⁾ valid before output clock
gpmc_clk high
F22 t_{h(clkH-waitV)}
Hold time, input wait gpmc_wait[x]⁽¹⁾
valid after output clock gpmc_clk
high
Industrial extended
temperature
(-40°C to 125°C)
All other temperature ranges
(1) In gpmc_wait[x], x is equal to 0 or 1.
OPP100
MIN MAX
3.2
OPP50
MIN MAX
13.2
4.74
4.74
4.74
2.75
3.2
13.2
4.74
4.74
4.74
2.75
UNIT
ns
ns
ns
ns
110 Peripheral Information and Timings
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