AMIC110 Datasheet, PDF (132/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
The device has a dedicated interface to mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM. It supports
JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit
data path to external SDRAM memory.
For more details on the mDDR(LPDDR), DDR2, DDR3, and DDR3L memory interface, see the EMIF
section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
7.7.2.1 mDDR (LPDDR) Routing Guidelines
It is common to find industry references to mobile double data rate (mDDR) when discussing JEDEC
defined low-power double-data rate (LPDDR) memory devices. The following guidelines use LPDDR when
referencing JEDEC defined low-power double-data rate memory devices.
7.7.2.1.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the LPDDR memory interface are shown in Table 7-16 and
Figure 7-18.
Table 7-16. Switching Characteristics for LPDDR Memory Interface
NO.
PARAMETER
MIN
MAX UNIT
1
t_{c(DDR_CK)}
t_{c(DDR_CKn)}
Cycle time, DDR_CK and DDR_CKn
5
(1)
ns
(1) The JEDEC JESD209B specification only defines the maximum clock period for LPDDR333 and faster speed bin LPDDR memory
devices. To determine the maximum clock period, see the respective LPDDR memory data sheet.
1
DDR_CK
DDR_CKn
Figure 7-18. LPDDR Memory Interface Clock Timing
7.7.2.1.2 LPDDR Interface
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the
need for a complex timing closure process. For more information regarding the guidelines for using this
LPDDR specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This
application report provides generic guidelines and approach. All the specifications provided in the data
manual take precedence over the generic guidelines and must be adhered to for a reliable LPDDR
interface operation.
7.7.2.1.2.1 LPDDR Interface Schematic
Figure 7-19 shows the schematic connections for 16-bit interface on the AMIC110 device using one x16
LPDDR device. The AMIC110 LPDDR memory interface only supports 16-bit-wide mode of operation. The
AMIC110 device can only source one load connected to the DQS[x] and DQ[x] net class signals and one
load connected to the CK and ADDR_CTRL net class signals. For more information related to net classes,
see Section 7.7.2.1.2.8.
132 Peripheral Information and Timings
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