AMIC110 Datasheet, PDF (129/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
Table 7-15. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
NO.
PARAMETER
OPP100
MIN
MAX
OPP50
UNIT
MIN
MAX
t_R(d)
t_F(d)
GNF0 t_w(wenV)
GNF1 t_d(csnV-wenV)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
Pulse duration, output write enable gpmc_wen
valid
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output write enable gpmc_wen valid
2
2
A⁽¹⁾
B⁽²⁾ – 0.2 B⁽²⁾ + 2.0
A⁽¹⁾
B⁽²⁾ – 5
2 ns
2 ns
ns
B⁽²⁾ + 5 ns
GNF2 t_w(cleH-wenV)
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle high to
output write enable gpmc_wen valid
C⁽³⁾ – 0.2 C⁽³⁾ + 2.0
C⁽³⁾ – 5
C⁽³⁾ + 5 ns
GNF3 t_w(wenV-dV)
Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid
D⁽⁴⁾ – 0.2 D⁽⁴⁾ + 2.0
D⁽⁴⁾ – 5
D⁽⁴⁾ + 5 ns
GNF4 t_w(wenIV-dIV)
Delay time, output write enable gpmc_wen
invalid to output data gpmc_ad[15:0] invalid
E⁽⁵⁾ – 0.2
E⁽⁵⁾ + 5
E⁽⁵⁾ – 5
E⁽⁵⁾ + 5 ns
GNF5 t_{w(wenIV-cleIV)}
Delay time, output write enable gpmc_wen
invalid to output lower-byte enable and command
latch enable gpmc_be0n_cle invalid
F⁽⁶⁾ – 0.2
F⁽⁶⁾ + 2.0
F⁽⁶⁾ – 5
F⁽⁶⁾ + 5 ns
GNF6 t_{w(wenIV-csnIV)}
Delay time, output write enable gpmc_wen
invalid to output chip select gpmc_csn[x]⁽¹³⁾
invalid
G⁽⁷⁾ – 0.2 G⁽⁷⁾ + 2.0
G⁽⁷⁾ – 5
G⁽⁷⁾ + 5 ns
GNF7 t_w(aleH-wenV)
Delay time, output address valid and address
latch enable gpmc_advn_ale high to output write
enable gpmc_wen valid
C⁽³⁾ – 0.2 C⁽³⁾ + 2.0
C⁽³⁾ – 5
C⁽³⁾ + 5 ns
GNF8 t_{w(wenIV-aleIV)}
GNF9 t_c(wen)
GNF10 t_d(csnV-oenV)
GNF13 t_w(oenV)
GNF14 t_c(oen)
GNF15 t_{w(oenIV-csnIV)}
Delay time, output write enable gpmc_wen
invalid to output address valid and address latch
enable gpmc_advn_ale invalid
Cycle time, write
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output enable gpmc_oen valid
Pulse duration, output enable gpmc_oen valid
Cycle time, read
F⁽⁶⁾ – 0.2 F⁽⁶⁾ + 2.0
I⁽⁹⁾ – 0.2
L⁽¹¹⁾
H⁽⁸⁾
I⁽⁹⁾ + 2.0
K⁽¹⁰⁾
F⁽⁶⁾ – 5
I⁽⁹⁾ – 5
L⁽¹¹⁾
F⁽⁶⁾ + 5 ns
H⁽⁸⁾ ns
I⁽⁹⁾ + 5 ns
K⁽¹⁰⁾
ns
ns
Delay time, output enable gpmc_oen invalid to
output chip select gpmc_csn[x]⁽¹³⁾ invalid
M⁽¹²⁾ – 0.2 M⁽¹²⁾ + 2.0 M⁽¹²⁾ – 5 M⁽¹²⁾ + 5
ns
(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾
(5) E = ((WrCycleTime – WEOffTime) × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾
(6) F = ((ADVWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
(7) G = ((CSWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾
(9) I = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾
(12) M = ((CSRdOffTime – OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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