AMIC110 Datasheet, PDF (142/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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7.7.2.2 DDR2 Routing Guidelines
7.7.2.2.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. Table 7-28 and
Figure 7-24 show the switching characteristics and timing diagram for the DDR2 memory interface.
Table 7-28. Switching Characteristics for DDR2 Memory Interface
NO.
PARAMETER
MIN
MAX UNIT
1
t_{c(DDR_CK)}
t_{c(DDR_CKn)}
Cycle time, DDR_CK and DDR_CKn
3.75
8⁽¹⁾
ns
(1) The JEDEC JESD79-2F specification defines the maximum clock period of 8 ns for all standard-speed bin DDR2 memory devices.
Therefore, all standard-speed bin DDR2 memory devices are required to operate at 125 MHz.
1
DDR_CK
DDR_CKn
Figure 7-24. DDR2 Memory Interface Clock Timing
7.7.2.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This application
report provides generic guidelines and approach. All the specifications provided in the data manual take
precedence over the generic guidelines and must be adhered to for a reliable DDR2 interface operation.
7.7.2.2.2.1 DDR2 Interface Schematic
Figure 7-25 shows the schematic connections for 16-bit interface on the AMIC110 device using one x16
DDR2 device and Figure 7-26 shows the schematic connections for 16-bit interface on the AMIC110
device using two x8 DDR2 devices. The AMIC110 DDR2 memory interface only supports 16-bit-wide
mode of operation. The AMIC110 device can only source one load connected to the DQS[x] and DQ[x] net
class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more
information related to net classes, see Section 7.7.2.2.2.8.
142 Peripheral Information and Timings
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