 English |
|
|
|
|
|
|
|
| AMIC110 Datasheet, PDF (135/214 Pages) Texas Instruments – Sitara Processors | |||
| |||
| ◁ |
www.ti.com
AMIC110
SPRS971A â AUGUST 2016 â REVISED SEPTEMBER 2016
Complete stackup specifications are provided in Table 7-19.
Table 7-19. PCB Stackup Specifications(1)
NO.
PARAMETER
MIN
TYP
MAX UNIT
1 PCB routing and plane layers
4
2 Signal routing layers
2
3 Full ground layers under LPDDR routing region
1
4 Number of ground plane cuts allowed within LPDDR routing region
0
5 Full VDDS_DDR power reference layers under LPDDR routing region
1
6
Number of layers between LPDDR routing layer and reference ground
plane
0
7 PCB routing feature size
4
mils
8 PCB trace width, w
9 PCB BGA escape via pad size(2)
10 PCB BGA escape via hole size(2)
11 Single-ended impedance, Zo(3)
12 Impedance control(4)(5)
Zo-5
4
mils
18
20 mils
10
mils
50
75 Ω
Zo
Zo+5 Ω
(1) For the LPDDR device BGA pad size, see the LPDDR device manufacturer documentation.
(2) A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to the
AMIC110 device.
(3) Zo is the nominal singled-ended impedance selected for the PCB.
(4) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(5) Tighter impedance control is required to ensure flight time skew is minimal.
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AMIC110
Peripheral Information and Timings 135
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese