AMIC110 Datasheet, PDF (167/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7.7.2.3.4.2 One DDR3 Device
One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as
one 16-bit bank.
7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 7-44 shows the topology of the CK net classes and Figure 7-45 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR3 Differential CK Input Buffer
+–
AMIC110
+
Differential Clock
Output Buffer
–
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A2
AT
Cac
Rcp
0.1 µF
A1
A2
AT
Routed as Differential Pair
Copyright © 2016, Texas Instruments Incorporated
Figure 7-44. CK Topology for One DDR3 Device
DDR3 Address and Control Input Buffers
AMIC110
Address and Control
Output Buffer
Address and Control
Terminator
Rtt
A1
A2
AT
Vtt
Copyright © 2016, Texas Instruments Incorporated
Figure 7-45. ADDR_CTRL Topology for One DDR3 Device
Copyright © 2016, Texas Instruments Incorporated
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