AMIC110 Datasheet, PDF (78/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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5.7 DC Electrical Characteristics
NOTE
The eCAP module is not supported for this family of devices, but the "eCAP" name is still
present in some terminal names.
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)⁽¹⁾
PARAMETER
MIN
NOM
MAX UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A
2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD
R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM
0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins
V_IH
High-level input voltage
0.65 ×
VDDS_DDR
V
V_IL
Low-level input voltage
0.35 ×
VDDS_DDR
V
V_HYS
V_OH
Hysteresis voltage at an input
High level output voltage, driver enabled, pullup or
pulldown disabled
I_OH = 8 mA
0.07
VDDS_DDR –
0.4
0.25 V
V
V_OL
Low level output voltage, driver enabled, pullup or
pulldown disabled
I_OL = 8 mA
0.4 V
Input leakage current, Receiver disabled, pullup or pulldown inhibited
10
I_I
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–240
80
–80 µA
240
Total leakage current through the terminal connection of a driver-receiver
I_OZ
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
10 µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A
2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD
R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM
0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins (DDR2 - SSTL Mode)
V_IH
High-level input voltage
DDR_VREF +
0.125
V
V_IL
Low-level input voltage
DDR_VREF –
0.125
V
V_HYS
Hysteresis voltage at an input
N/A
V
V_OH
High-level output voltage, driver enabled, pullup or
pulldown disabled
I_OH = 8 mA
VDDS_DDR –
0.4
V
V_OL
Low-level output voltage, driver enabled, pullup or
pulldown disabled
I_OL = 8 mA
0.4 V
Input leakage current, Receiver disabled, pullup or pulldown inhibited
10
I_I
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–240
80
–80 µA
240
Total leakage current through the terminal connection of a driver-receiver
I_OZ
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
10 µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A
2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD
R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM
0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins (DDR3 - HSTL Mode)
VDDS_DDR =
DDR_VREF +
1.5 V
0.1
V_IH
High-level input voltage
VDDS_DDR =
DDR_VREF +
V
1.35 V
0.09
V_IL
Low-level input voltage
VDDS_DDR =
1.5 V
VDDS_DDR =
1.35 V
DDR_VREF –
0.1
V
DDR_VREF –
0.09
V_HYS
Hysteresis voltage at an input
N/A
V
V_OH
High-level output voltage, driver enabled, pullup or
pulldown disabled
I_OH = 8 mA
VDDS_DDR –
0.4
V
V_OL
Low-level output voltage, driver enabled, pullup or
pulldown disabled
I_OL = 8 mA
0.4 V
78
Specifications
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