AMIC110 Datasheet, PDF (105/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7 Peripheral Information and Timings
The AMIC110 device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AMIC110 terminals can
multiplex up to eight signal functions. Although there are many combinations of pin multiplexing that are
possible, only a certain number of sets, called I/O Sets, are valid due to timing limitations. These valid I/O
Sets were carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system
designer select the appropriate pin-multiplexing configuration for their AMIC110-based product design.
The Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the
pin-multiplexing configuration selected for a design only uses valid I/O Sets supported by the AMIC110
device.
7.1 Parameter Information
The data provided in the following Timing Requirements and Switching Characteristics tables assumes the
device is operating within the Recommended Operating Conditions defined in Section 5, unless otherwise
noted.
7.1.1 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing or decreasing such delays. TI recommends using the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control
register is configured for fast mode (0b).
For the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, it is not necessary to use the IBIS
models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the
routing rules to ensure the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface timings are met.
7.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic
manner.
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