AMIC110 Datasheet, PDF (102/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
www.ti.com
6.2.2.4 OSC1 LVCMOS Digital Clock Source
Figure 6-15 shows the recommended oscillator connections when OSC1 of the ZCE package is connected
to an LVCMOS square-wave digital clock source and Figure 6-16 shows the recommended oscillator
connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock
source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. The ground for the
LVCMOS clock source and VSS_RTC of the ZCZ package should be connected directly to the nearest
PCB digital ground (VSS). In this mode of operation, the RTC_XTALOUT terminal should not be used to
source any external components. The PCB design should provide a mechanism to disconnect the
RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1
through the RTC_XTALOUT terminal.
The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is
disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level
which may increase leakage current through the oscillator input buffer.
VDDS_RTC
RTC_XTALIN
AMIC110
(ZCE Package)
RTC_XTALOUT
LVCMOS
Digital
N/C
Clock
Source
Copyright © 2016, Texas Instruments Incorporated
Figure 6-15. OSC1 (ZCE Package) LVCMOS Circuit Schematic
VDDS_RTC
RTC_XTALIN
AMIC110
(ZCZ Package)
VSS_RTC RTC_XTALOUT
LVCMOS
Digital
N/C
Clock
Source
Copyright © 2016, Texas Instruments Incorporated
Figure 6-16. OSC1 (ZCZ Package) LVCMOS Circuit Schematic
Table 6-7. OSC1 LVCMOS Reference Clock Requirements
NAME
DESCRIPTION
MIN
TYP MAX UNIT
Frequency, LVCMOS reference clock
32.768
kHz
ƒ_{(RTC_XTALIN)}
Frequency, LVCMOS reference clock
Maximum RTC error =
10.512 minutes/year
–20
stability and tolerance⁽¹⁾
Maximum RTC error = 26.28
minutes/year
–50
20 ppm
50 ppm
t_{dc(RTC_XTALIN)}
t_{jpp(RTC_XTALIN)}
t_{R(RTC_XTALIN)}
t_{F(RTC_XTALIN)}
Duty cycle, LVCMOS reference clock period
Jitter peak-to-peak, LVCMOS reference clock period
Time, LVCMOS reference clock rise
Time, LVCMOS reference clock fall
45%
–1%
55%
1%
5 ns
5 ns
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
102 Power and Clocking
Submit Documentation Feedback
Product Folder Links: AMIC110
Copyright © 2016, Texas Instruments Incorporated