C8051F52X_12 Datasheet, PDF (99/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction, and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Table 10.1. Interrupt Summary
Interrupt Source
Interrupt Priority
Vector Order
Pending Flag
Enable
Flag
Priority
Control
Reset
0x0000 Top
External Interrupt 0(INT0) ^{0x0003 0}
None
IE0 (TCON.1)
N/A N/A Always
Enabled
Always
Highest
Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow
0x000B 1
TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1(INT0) ^{0x0013 2}
IE1 (TCON.3)
Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
0x001B 3
TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
UART
Timer 2 Overflow
SPI0
0x0023
0x002B
0x0033
ADC0 Window Compara- 0x003B
tor
4
RI0 (SCON0.0)
Y N ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
5
TF2H (TMR2CN.7) Y N ET2 (IE.5) PT2 (IP.5)
TF2L (TMR2CN.6)
6
SPIF (SPI0CN.7) Y N ESPI0
PSPI0
WCOL (SPI0CN.6)
(IE.6)
(IP.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
7
AD0WINT
Y N EWADC0 PWADC0
(ADC0CN.3)
(EIE1.0) (EIP1.0)
ADC0 End of Conversion 0x0043
8 AD0INT (ADC0CN.5) Y N EADC0 PADC0
(EIE1.1) (EIP1.1)
Programmable Counter 0x004B 9
Array
CF (PCA0CN.7) Y N EPCA0 PPCA0
CCFn (PCA0CN.n)
(EIE1.2) (EIP1.2)
Comparator Falling Edge 0x0053 10 CP0FIF (CPT0CN.4) N N
Comparator Rising Edge 0x005B 11 CP0RIF (CPT0CN.5) N N
LIN Interrupt
0x0063 12
LININT (LINST.3) N N*
Voltage Regulator Dropout 0x006B 13
N/A
N/A N/A
Port Match
0x0073 14
N/A
N/A N/A
Note: Software must set the RSTINT bit (LINCTRL.3) to clear the LININT flag.
ECPF
(EIE1.3)
ECPR
(EIE1.4)
ELIN
(EIE1.5)
EREG0
(EIE1.6)
EMAT
(EIE1.7)
PCPF
(EIP1.3)
PCPR
(EIP1.4)
PLIN
(EIP1.5)
PREG0
(EIP1.6)
PMAT
(EIP1.7)
Rev. 1.4
99