C8051F52X_12 Datasheet, PDF (6/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
19. Programmable Counter Array (PCA0)................................................................ 195
19.1. PCA Counter/Timer ....................................................................................... 196
19.2. Capture/Compare Modules ........................................................................... 197
19.2.1. Edge-triggered Capture Mode............................................................... 198
19.2.2. Software Timer (Compare) Mode.......................................................... 199
19.2.3. High Speed Output Mode...................................................................... 200
19.2.4. Frequency Output Mode ....................................................................... 201
19.2.5. 8-Bit Pulse Width Modulator Mode........................................................ 202
19.2.6. 16-Bit Pulse Width Modulator Mode...................................................... 203
19.3. Watchdog Timer Mode .................................................................................. 203
19.3.1. Watchdog Timer Operation ................................................................... 204
19.3.2. Watchdog Timer Usage ........................................................................ 205
19.4. Register Descriptions for PCA....................................................................... 206
20. Device Specific Behavior .................................................................................... 210
20.1. Device Identification ...................................................................................... 210
20.2. Reset Pin Behavior........................................................................................ 211
20.3. Reset Time Delay .......................................................................................... 211
20.4. VDD Monitors and VDD Ramp Time ............................................................. 211
20.5. VDD Monitor (VDDMON0) High Threshold Setting ....................................... 212
20.6. Reset Low Time............................................................................................. 212
20.7. Internal Oscillator Suspend Mode ................................................................. 212
20.8. UART Pins..................................................................................................... 213
20.9. LIN ................................................................................................................. 213
20.9.1. Stop Bit Check ...................................................................................... 213
20.9.2. Synch Break and Synch Field Length Check........................................ 213
21. C2 Interface .......................................................................................................... 214
21.1. C2 Interface Registers................................................................................... 214
21.2. C2 Pin Sharing .............................................................................................. 216
Document Change List.............................................................................................. 217
Contact Information................................................................................................... 220
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Rev. 1.4