C8051F52X_12 Datasheet, PDF (40/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
P0.2 1
P0.1 2
RST/C2CK 3
P0.0/V_REF 4
GND 5
V_DD
6
V_REGIN
7
P1.7 ⁸
P1.6 ⁹
P1.5 ¹⁰
20 P0.3
19 P0.4/TX
18 P0.5/RX
17 P0.6/C2D
16 P0.7/XTAL1
15 P1.0/XTAL2
14 _P1.1
13 _P1.2/CNVSTR
12 _P1.3
11 _P1.4
P0.2 1
P0.1 2
RST/C2CK 3
P0.0/V_REF 4
GND 5
V_DD
6
V_REGIN
7
P1.7 ⁸
P1.6 ⁹
P1.5 ¹⁰
Figure 3.4. TSSOP-20 Pinout Diagram (Top View)
20 P0.3/TX
19 P0.4/RX
18 P0.5
17 P0.6/C2D
16 P0.7/XTAL1
15 P1.0/XTAL2
14 _P1.1
13 _P1.2/CNVSTR
12 _P1.3
11 _P1.4
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20)
Name Pin Numbers Type Description
P0.2
P0.1
RST/
C2CK
‘F53xA ‘F53x
‘F53x-C
1
1 D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
2
2 D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
3
3 D I/O Device Reset. Open-drain output of internal POR or V_DD monitor.
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
D I/O
reset, as defined in Table 2.8 on page 32. A 1 k pullup to V_RE-
GIN ^{is recommended. See Reset Sources Section for a complete}
description.
P0.0/
Clock signal for the C2 Debug Interface.
4
4 D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
V_REF
A O or External V_REF Input. See V_REF Section.
D In
GND
5
5
Ground.
V_DD
6
6
Core Supply Voltage.
*Note: Please refer to Section “20. Device Specific Behavior” on page 210.
40
Rev. 1.4