C8051F52X_12 Datasheet, PDF (49/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Table 3.8. QFN-20 Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
4.00 BSC.
D2
2.55
2.70
2.85
e
0.50 BSC.
E
4.00 BSC.
E2
2.55
2.70
2.85
L
0.30
0.40
0.50
L1
0.00
—
0.15
aaa
—
—
0.15
bbb
—
—
0.10
ddd
—
—
0.05
eee
—
—
0.08
Z
—
0.43
—
Y
—
0.18
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD except for
custom features D2, E2, Z, Y, L, and L1, which are toleranced per supplier
designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.4
49