C8051F52X_12 Datasheet, PDF (73/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Important Note About the V_REF Pin: Port pin P0.0 is used as the external V_REF input and as an output for
the internal V_REF. When using either an external voltage reference or the internal reference circuitry, P0.0
should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P0.0 as an ana-
log pin, clear Bit 0 in register P0MDIN to 0. To configure the Crossbar to skip P0.0, set Bit 0 in register
P0SKIP to 1. Refer to Section “13. Port Input/Output” on page 120 for complete Port I/O configuration
details.
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temper-
ature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor
result in meaningless data.
SFR Definition 5.1. REF0CN: Reference Control
R/W
R/W
Reserved Reserved
Bit7
Bit6
R/W
ZTCEN
Bit5
R/W
REFLV
Bit4
R/W
REFSL
Bit3
R/W
TEMPE
Bit2
R/W
BIASE
Bit1
R/W
REFBE
Bit0
Reset Value
00000000
SFR Address:
0xD1
Bits7–6: RESERVED. Read = 00b. Must write 00b.
Bit5: ZTCEN: Zero-TempCo Bias Enable Bit*.
0: ZeroTC Bias Generator automatically enabled when needed.
1: ZeroTC Bias Generator forced on.
Bit4: REFLV: Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference.
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.2 V.
Bit3: REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: V_REF pin used as voltage reference.
1: V_DD used as voltage reference.
Bit2: TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1: BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Analog Bias Generator automatically enabled when needed.
1: Internal Analog Bias Generator on.
Bit0: REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the V_REF pin.
*Note: See Section “20.7. Internal Oscillator Suspend Mode” on page 212 for a note related to the ZTCEN bit in
older silicon revisions.
Rev. 1.4
73