C8051F52X_12 Datasheet, PDF (46/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20)
Name Pin Numbers Type Description
RST/
C2CK
‘F53xA ‘F53x
‘F53x-C
1
1
D I/O
D I/O
Device Reset. Open-drain output of internal POR or V_DD monitor.
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.8 on page 32. A 1 k pullup to V_RE-
GIN ^{is recommended. See Reset Sources Section for a complete}
description.
P0.0/
Clock signal for the C2 Debug Interface.
2
2 D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
V_REF
GND
V_DD
V_REGIN
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2/
A O or _{External VREF Input. See VREF Section.}
D In
3
3
Ground.
4
4
Core Supply Voltage.
5
5
On-Chip Voltage Regulator Input.
6
6 D I/O or Port 1.7. See Port I/O Section for a complete description.
A In
7
7 D I/O or Port 1.6. See Port I/O Section for a complete description.
A In
8
8 D I/O or Port 1.5. See Port I/O Section for a complete description.
A In
9
9 D I/O or Port 1.4. See Port I/O Section for a complete description.
A In
10 10 D I/O or Port 1.3. See Port I/O Section for a complete description.
A In
11 11 D I/O or Port 1.2. See Port I/O Section for a complete description.
A In
CNVSTR
D In External Converter start input for the ADC0, see Section “4. 12-
Bit ADC (ADC0)” on page 52 for a complete description.
P1.1
12 12 D I/O or Port 1.1. See Port I/O Section for a complete description.
A In
Note: Please refer to Section “20. Device Specific Behavior” on page 210.
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Rev. 1.4