C8051F52X_12 Datasheet, PDF (205/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
19.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
 Disable the WDT by writing a 0 to the WDTE bit.
 Select the desired PCA clock source (with the CPS2-CPS0 bits).
 Load PCA0CPL2 with the desired WDT update offset value.
 Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
 Enable the WDT by setting the WDTE bit to 1.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 19.3 lists some example timeout intervals for typical
system clocks.
Table 19.3. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
PCA0CPL2 Timeout Interval (ms)
24,500,000
255
24,500,000
128
24,500,000
32
18,432,000
255
18,432,000
128
18,432,000
32
11,059,200
255
11,059,200
128
11,059,200
32
3,062,500
255
3,062,500
128
3,062,500
32
191,406²
255
191,406²
128
191,406²
32
32,000
255
32,000
128
32,000
32
32.1
16.2
4.1
42.7
21.5
5.5
71.1
35.8
9.2
257
129.5
33.1
4109
2070
530
24576
12384
3168
Notes:
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L
value of 0x00 at the update time.
2. Internal oscillator reset frequency.
Rev. 1.4
205