C8051F52X_12 Datasheet, PDF (91/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 8.7. PCON: Power Control
R/W
R/W
R/W
R/W
R/W
R/W
Reserved Reserved Reserved Reserved Reserved Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
STOP
Bit1
R/W
Reset Value
IDLE 00000000
Bit0
SFR Address: 0x87
Bits7–2: RESERVED.
Bit1: STOP: STOP Mode Select.
Writing a 1 to this bit will place the CIP-51 into STOP mode. This bit will always read 0.
1: CIP-51 forced into power-down mode. (Turns off internal oscillator).
Bit0: IDLE: IDLE Mode Select.
Writing a 1 to this bit will place the CIP-51 into IDLE mode. This bit will always read 0.
1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
and all peripherals remain active.)
Rev. 1.4
91