C8051F52X_12 Datasheet, PDF (24/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
1.9. Port Input/Output
C8051F52x/F52xA/F53x/F53xA devices include up to 16 I/O pins. Port pins are organized as two byte-
wide ports. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be
configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or
open-drain operation. The “weak pullups” that are fixed on typical 8051 devices may be globally disabled
to save power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip coun-
ter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the
port pins using the Crossbar control registers. This allows the user to select the exact mix of general-pur-
pose port I/O, digital, and analog resources needed for the application.
XBR0, XBR1,
PnSKIP Registers
P0MASK, P0MATCH
P1MASK, P1MATCH
Registers
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
LIN
CP0
2
Outputs
SYSCLK
PCA
7
2
T0, T1
8
P0 ^(P0.0-P0.7)
8
P1 ^(P1.0-P1.7*)
Priority
Decoder
PnMDOUT,
PnMDIN Registers
Digital
Crossbar
8
P0
I/O
Cells
8
P1
I/O
Cells
P0.0
P0.7
P1.0*
P1.7*
*Available in 'F53x/'F53xA
devices
Figure 1.9. Port I/O Functional Block Diagram
24
Rev. 1.4