C8051F52X_12 Datasheet, PDF (212/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
20.5. V_DD Monitor (VDDMON0) High Threshold Setting
The calibration behavior of the internal voltage regulator (REG0) and its impact on V_DD monitor
(VDDMON0) high threshold setting differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
The following note applies to Revision A and Revision B devices: The output of the internal voltage reg-
ulator (REG0) is calibrated by the MCU immediately after any reset event. The output of the un-calibrated
internal regulator could be below the high threshold setting (V_RST-HIGH) of the V_DD Monitor (VDDMON0). If
this is the case and the V_DD Monitor is set to the high threshold setting and if the MCU receives a non-
power on reset, the MCU will remain in reset until a power-on reset (POR) occurs (i.e. V_DD Monitor will
keep the device in reset). A POR will force the V_DD Monitor to the low threshold setting which is guaran-
teed to be below the un-calibrated output of the internal regulator. The device will then exit reset and
resume normal operation. It is for this reason Silicon Labs strongly recommends that the V_DD Monitor is
always left in the low threshold setting (i.e., default value upon POR).
When programming the Flash in-system, the V_DD Monitor (VDDMON0) must be set to the high threshold
setting. For the highest system reliability, the time the V_DD Monitor is set to the high threshold setting
should be minimized (e.g., setting the V_DD Monitor to the high threshold setting just before the Flash write
operation and then changing it back to the low threshold setting immediately after the Flash write opera-
tion).
The following note applies to Revision C devices: The output of the internal voltage regulator (REG0) is
calibrated by the MCU immediately after a power-on reset (POR). This calibrated output setting will stay
calibrated through any type of reset other than POR. Because of this change in behavior of REG0, the “low
threshold” recommendation noted above for Revision A and Revision B devices does not apply to Revision
C devices; the V_DD Monitor (VDDMON0) can be set to the high threshold as needed depending on the
application.
20.6. Reset Low Time
The maximum reset low time differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
Reset low time is the duration for which the RST pin is driven low by an external circuit while power is
applied to the device. On Revision A and Revision B devices with assembly build date code earlier than
1124 (year 2011, work week 24), the reset low time should be a maximum of 1 second. For longer reset
low times, a percentage of devices within a narrow range of temperatures (a 5 to 10 C window) may
“lock up” and fail to execute code. The condition is cleared only by cycling power.
Revision B devices with assembly date code 1124 or later and Revision C devices do not have any restric-
tions on reset low time.
20.7. Internal Oscillator Suspend Mode
The required bias setting for the internal oscillator before entering suspend mode differs between the sili-
con revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, firmware must set the ZTCEN bit in REF0CN (SFR Definition 5.1)
before entering suspend mode. If ZTCEN is not set to 1, there is a low probability of the device remaining
in suspend even when a wake-up condition is triggered. On Revision C devices, this bit need not be set to
1 before entering suspend mode.
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Rev. 1.4