C8051F52X_12 Datasheet, PDF (164/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)
Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto-
col. For more information about the LIN protocol, including specifications, please refer to the LIN consor-
tium (http://www.lin-subbus.org/).
LIN is an asynchronous, serial communications interface used primarily in automotive networks. The Sili-
con Laboratories LIN controller is compliant to the 2.1 Specification, implements a complete hardware LIN
interface, and includes the following features:
 Selectable Master and Slave modes.
 Automatic baud rate option in slave mode
 The internal oscillator is accurate to within 0.5% of 24.5 MHz across the entire temperature range and
for VDD voltages greater than or equal to the minimum output of the on-chip voltage regulator, so an
external oscillator is not necessary for master mode operation for most systems.
Note: The minimum system clock (SYSCLK) required when using the LIN peripheral is 8 MHz.
C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A
LIN Controller
LIN Data
Registers
LIN Control
Registers
Indirectly Addressed Registers
8051 MCU Core
LINADDR
LINDATA
TX
Control State Machine
RX
LINCF
Figure 17.1. LIN Block Diagram
The LIN peripheral has four main components:
1. LIN Access Registers—Provide the interface between the MCU core and the LIN peripheral.
2. LIN Data Registers—Where transmitted and received message data bytes are stored.
3. LIN Control Registers—Control the functionality of the LIN interface.
4. Control State Machine and Bit Streaming Logic—Contains the hardware that serializes mes-
sages and controls the bus timing of the controller.
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Rev. 1.4