C8051F52X_12 Datasheet, PDF (192/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
18.2.3. External Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 2 can be
clocked from the system clock, or the system clock divided by 12, depending on the T2ML (CKCON.4) and
T2XCLK bits. When a capture event is generated, the contents of Timer 2 (TMR2H:TMR2L) are loaded
into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. A capture event is gener-
ated by the falling edge of the clock source being measured, which is the external oscillator/8. By recording
the difference between two successive timer capture values, the external oscillator frequency can be
determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the capture
clock to achieve an accurate reading. Timer 2 should be in 16-bit auto-reload mode when using Capture
Mode.
For example, if T2ML = 1b and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every external
clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two successive captures is
5984, then the external clock frequency is:
2_----4_---._-5_{-----M-----H----z--}
5984  8
=
0.032754
MHz
or 32.754
kHz
This mode allows software to determine the external oscillator frequency when an RC network or capacitor
is used to generate the clock source.
External Osc. / 8
SYSCLK / 12
T2XCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
SYSCLK
1
1
0
TR2
0
External Osc. / 8
TCLK
TMR2H
Capture
TMR2L
TMR2RLH TMR2RLL
TF2H
TF2L
TF2LEN
TF2CEN
TR2
TR2CLK
T2XCLK
Interrupt
TF2CEN
Figure 18.6. Timer 2 Capture Mode Block Diagram
192
Rev. 1.4