C8051F52X_12 Datasheet, PDF (204/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
19.3.1. Watchdog Timer Operation
While the WDT is enabled:
 PCA counter is forced on.
 Writes to PCA0L and PCA0H are not allowed.
 PCA clock source bits (CPS2-CPS0) are frozen.
 PCA Idle control bit (CIDL) is frozen.
 Module 2 is forced into software timer mode.
 Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 19.10).
PCA0MD
CWW CCCE
I D D PPPC
DT L SSSF
LEC 210
K
PCA0CPH2
8-bit
Enable ^Comparator
Match
Reset
PCA0CPL2
8-bit Adder
PCA0H
PCA0L Overflow
Write to
PCA0CPH2
Adder
Enable
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 19.4, where PCA0L is the value of the PCA0L register
at the time of the update.
Offset = 256  PCA0CPL2 + 256 – PCA0L
Equation 19.4. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
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Rev. 1.4