C8051F52X_12 Datasheet, PDF (187/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 18.2. TMOD: Timer Mode
R/W
GATE1
Bit7
R/W
C/T1
Bit6
R/W
T1M1
Bit5
R/W
T1M0
Bit4
R/W
GATE0
Bit3
R/W
C/T0
Bit2
R/W
T0M1
Bit1
R/W
Reset Value
T0M0 ^00000000
Bit0
SFR Address: 0x89
Bit7: GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT0 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT0 is active as defined by bit IN1PL in register
IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
Bit6: C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5–4: T1M1–T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
0
0
1
1
T1M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with auto-reload
Mode 3: Timer 1 inactive
Bit3: GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in register
IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
Bit2: C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1–0: T0M1–T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1
0
0
1
1
T0M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with auto-reload
Mode 3: Two 8-bit counter/timers
Rev. 1.4
187